1. Field of the Invention
The present invention relates to the field of level translation circuits, and more specifically level translation circuits responsive to a logic signal to control a semiconductor switch operative at a substantially different voltage level.
2. Prior Art
In a variety of circuits, it is desirable to use a logic control signal to control a semiconductor switch operative at a substantially different voltage reference level. For example, in a motor driver application, the switch is located on the positive power terminal whereas the logic signals to control this switch are referenced to the negative power terminal.
Another example of this is in step-down topology DC to DC converters. FIG. 1 shows schematically the switch drive topology of a typical step-down DC-DC converter. For switching speed and low on resistance, it is highly preferred to use an n-channel MOSFET switch for the high side switch S1. The low side switch S2 could be a diode, or to reduce the on voltage drop across the element, could be more preferably an actively driven n-channel MOSFET. When an n-channel MOSFET is used for S1, note that to turn it on, a voltage higher than the input voltage VIN is required. On the other hand, this voltage cannot be too high or too low (negative) due to restrictions on the maximum gate to source potential of the MOSFET.
As shown schematically in FIG. 2, one scheme for driving the gate voltage that has been used in the past is to generate a voltage that is actually referred to the voltage of the source of n-channel MOSFET S1. The potential V(C1) (the voltage of node 2 minus the voltage of node 1 in FIG. 2) is developed across reservoir capacitor C1 by diode D1, charging C1 to V3 minus the forward conduction voltage drop of diode D1 every time node 1 is switched to ground.
The gate driver for MOSFET S1 turns the MOSFET on by connecting S1's gage to node 2, and turns S1 off by connecting S1's gate to node 1 (See FIG. 3 for waveforms). Note that in actuality, node 1 is at the potential VIN when S1 is on and at zero potential when S1 is off and switch S2 is on. Therefore, node 2 always flies up and down as S1 is turned on and off at a very high voltage slew rate. Furthermore, since the reservoir element is a capacitor, any current drain during the off state (both switches S1 and S2 non-conducting) will cause this circuit to be useless. This is because in modern DC--DC converters, there are long periods of zero load current resulting in no switching of S1 and S2. The reservoir capacitor C1 therefore cannot be discharged in switch S1's off state for the circuit to remain operative on command.
If switch S2 is going to be an active n-channel MOSFET, then there is one other requirement. The turn on and turn off times of S1 and S2 must be very well controlled to prevent them from being on at the same time, even if momentarily.
Prior art solutions to these problems have been complicated, and in general not monolithic solutions. Some applications use pulse transformers, some use capacitive coupling techniques, etc. But none of these really result in a solution that can be integrated on one chip for reduced cost and improved reliability.
The problem addressed by the present invention may be summarized as one of performing level translation of a logic signal located at one reference level (zero volts in FIG. 2) to a logic signal at another level (node 1 in FIG. 2). Furthermore, the solution should be monolithic, should provide the level translation at high speed and also work reliably even if the controlled switch voltage is rapidly changing. There should also be no power consumption when the power switch is off. Finally, in applications where there are two active switches, the two switches must never be on at the same time, even if only momentarily.